The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed. Implementations of the present invention, however, are described with respect to a flash electrically erasable and programmable read-only memory (EEPROM), wherein the storage elements are floating gates, as exemplary.
It is common in current commercial products for each floating gate storage element of a flash EEPROM array to store a single bit of data by operating in a binary mode, where two ranges of threshold levels of the floating gate transistors are defined as storage levels. The threshold levels of a floating gate transistor correspond to ranges of charge levels stored on their floating gates. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each floating gate transistor. This is accomplished by defining more than two threshold levels as storage states for each floating gate transistor, four such states (2 bits of data per floating gate storage element) now being included in commercial products. More storage states, such as 16 states per storage element, are contemplated. Each floating gate memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow them to be clearly differentiated from one another. The trend towards lower power systems results in a smaller widow of available threshold voltages, further aggravating this problem.
This is true of the various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and Ser. No. 09/505,555, filed Feb. 17, 2000, and Ser. No. 09/667,344, filed Sep. 22, 2000.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935 and U.S. patent application Ser. No. 09/893,277, filed Jun. 27, 2001. Other examples are given in U.S. patent applications entitled “Highly Compact Non-Volatile Memory and Method Thereof”, by Raul-Adrian Cernea, and “Non-Volatile Memory and Method with Reduced Source Line Bias Errors”, by Raul-Adrian Cernea and Yan Li, both filed Sep. 24, 2002 and both hereby incorporated by this reference.
Occasionally, flash memory cells are known to suffer from poor subthreshold slope or weak transconductance. These cells are sometimes referred to as gm degraded cells and typically have an undesirable current-voltage (I-V) characteristic. The cells have a reduced conductivity, but more importantly their turn-off characteristics, defined by their subthreshold slope, are very poor. Thus, the cells are still conducting at gate voltages below the threshold voltage, meaning they have a greater capacity to be read incorrectly.
FIG. 1 compares a typical I-V curve from such a gm-degraded cell to a well-behaved cell, where the current is shown in a logarithmic scale. In this figure, a well-behaved, or “good”, cell is shown with the open squares and a “bad” cell with degraded transconductance is shown with the black diamonds. Both cells have been programmed to a target state defined by a drain-source current level IDS=I1 in response to a control gate voltage Vcg=V1. Aside from this point, the two curves differ, with the bad cell having a lower current for higher voltages (the degraded transconductance) and a higher current for lower Vcg values (the poor subthreshold slope part). These cells become worse as the memory is cycled and the cell characteristics can be improved if the cycling damage is allowed to relax. Thus, it is likely that some type of charge model, for example interface states, plays a role in causing the poor subthreshold slope and reduced transconductance. These cells can cause stored data to be corrupted if the subthreshold slope deteriorates to the point that the cell is still conducting even when the gate voltage is below the cell threshold. This significantly reduces the read margin and makes the cell very susceptible to “flipping bits” if the read conditions are varied. For example, the point I1-V1 were the lines cross would likely be determined by the program verify conditions corresponding to some memory state's target values, which will often differ by some margin from the control read voltage used for this state. Consequently, the bad cell's current level corresponding to this read voltage will differ from that of the good cell, even though they have both been programmed to the same state. In fact, this phenomenon is usually seen when memories fail after cycling due to some cells flipping from a programmed to an erased state. Additionally, it has been found that bad cells tend to drift form their programmed value at a faster rate than the good cells.
Although the discussion has been in terms of flash memory cells, more generally it will be true of any memory using a transistor based non-volatile storage element where the current-voltage properties determine the written data state, for example a dielectric storage element. A method to identify cells suffering from this phenomenon before they corrupt the stored data would be highly advantageous.